In devices having programmable resources, interconnect multiplexers are implemented to enable the connection of various circuits in an integrated circuit device. Conventional interconnect multiplexers implement N-type metal oxide semiconductor (NMOS) pass-gates that are controlled by single ended outputs of configuration memory cells. An on-chip power supply to memory cells is pulled to ground during start-up to avoid any current contentions in the circuit. This would ensure that memory cells would switch off all NMOS transistors in multiplexers during power-up. A P-type metal oxide semiconductor (PMOS) transistor at the multiplexer output would initialize an input to a first inverter to a “HIGH” state, and a half-latch on the first inverter would retain this state and drive a “HIGH” on the final output inverter.
However, conventional circuits reducing or preventing current contention will not work for pass-gates having PMOS transistors. That is, the powering down of the on-chip memory cell power supply to ground will not ensure that outputs of memory cells are at logic “LOW” state. Rather, they may be stuck at a threshold voltage above ground, and would require a half-latch, which will impact the signal rise time at the input to the first inverter and therefore affect performance. Further, the write margin into the half-latch impacts the yield because of write margins that vary due to process corner variations. It is desirable to provide multiplexers that minimize contention in an integrated circuit.